1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to semiconductor integrated circuit devices in which basic cells are regularly arranged, such as master-slice type semiconductor integrated circuit devices (gate arrays), and hybrid LSI circuit devices in which basic cells are formed on a chip together with standard cells, CPU cores and analog circuits.
For example, a master-slice type semiconductor integrated circuit device comprises basic cells arranged on a chip center area surrounded by chip peripheral areas. In the past, the basic cells were arranged in a wiring channel manner in which basic cell arrangement areas and wiring channel areas on the chip are separated from one another on the chip center area. Recently, in order to obtain an increased number of gates, there has been considerable activity in the development of master-slice type semiconductor integrated circuit devices of an SOG (Sea-Of-Gates) type. In the SOG type, a plurality of gate cells are arranged on the entire chip center area. In the master-slice type semiconductor integrated circuit devices, it is required that large-scale macrocells, such as a RAM and a ROM, be arranged together with logic unit cells, such as inverters and NAND circuits. In this regard, it is desirable that the basic cells of the master-slice type semiconductor integrated circuit devices have a structure which makes it possible to efficiently arrange the logic unit cells and macrocells.
FIG. 1 shows a conventional basic cell for the master-slice type semiconductor integrated circuit devices. The basic cell shown in FIG. 1 comprises N.sup.+ -type diffused regions 1-3, P.sup.+ -type diffused regions, and gate electrodes made of polysilicon. An n-type MOS transistor (hereinafter simply referred to as an nMOS transistor) 11 is formed by the N.sup.+ -type diffused regions 1 and 2, and the gate electrode 7. An nMOS transistor 12 is formed by the N.sup.+ -type diffused regions 2 and 3 and the gate electrode 8. A p-type MOS transistor (hereinafter simply referred to as a pMOS transistor) 13 is formed by the P.sup.+ -type diffused regions 4 and 5, and the gate electrode 9, and a pMOS transistor 14 is formed by the P.sup.+ -type diffused regions 5 and 6, and the gate electrode 10.
FIG. 2 shows another conventional basic cell for the master-slice type semiconductor integrated circuit devices (see U.S. Pat. No. 5,053,993). The basic cell shown in FIG. 2 comprises N.sup.+ -type diffused regions 15-23, P.sup.+ -type diffused regions 24-26, and gate electrodes 27-30 made of polysilicon. An nMOS transistor 31 is formed by the N.sup.+ -type diffused regions 15 and 16, and the gate electrode 27, and an nMOS transistor 32 is formed by the N.sup.+ -type diffused regions 16 and 17, and the gate electrode 28. A pMOS transistor 33 is formed by the P.sup.+ -type diffused regions 24 and 25, and the gate electrode 27, and a pMOS transistor 34 is formed by the P.sup.+ -type diffused regions 25 and 26 and the gate electrode.
An nMOS transistor 35 is formed by the N.sup.+ -type diffused regions 18 and 19, and the gate electrode 29, and an nMOS transistor 36 is formed by the N.sup.+ -type diffused regions 19 and 20 and the gate electrode 30. An nMOS transistor 37 is formed by the N.sup.+ -type diffused regions 21 and 22, and the gate electrode 29, and an nMOS transistor 38 is formed by the N.sup.+ -type diffused regions 22 and 23, and the gate electrode 30.
The basic cell shown in FIG. 2 is suitable for a two-port RAM. In this case, the nMOS transistors 31 and 32 and the pMOS transistors 33 and 34 form two inverters functioning as a memory cell, and the four nMOS transistors 35-38 form respective transfer gates for selectively connecting the memory cell to two pairs of bit lines. Generally, the nMOS transistors 35-38 have sizes smaller than those of the transistors 31-34 in order to prevent an erroneous read/write operation.
However, the conventional basic cell shown in FIG. 1 has disadvantages which will be described in detail later. The conventional basic cell shown in FIG. 2 has the following disadvantages. The basic cell shown in FIG. 2 is long in the longitudinal or traverse direction because of the presence of the nMOS transistors 35-38. Hence, the layout of wiring layers needs a large wiring pitch between adjacent wiring layers (channels), and has a small degree of freedom regarding the allocation of the logic unit cells and the formation of the wiring channel areas. Further, if a single-port RAM is formed using the basic cells as shown in FIG. 2, the basic cells cannot be efficiently used because some transistors are not used for forming the single-port RAM. The above-mentioned disadvantages hold true for hybrid LSIs having the basic cells, the standard cells, the CPU cores and analog circuits.